This invention generally relates to IC manufacture and assembly, and in particular to methods of producing semiconductor packages which are interconnectably mounted on underlying semiconductor package substrates.
Chip package interconnect systems are used by the semiconductor industry in the production of IC devices. Wire bonding and Tape Automated Bonding (TAB) are the most common chip interconnect methods used in the industry. However, the problems confronting wire bonding and TAB are becoming more apparent. Demands for increased I/O and electrical performance within smaller, denser chips are pushing wire bond and TAB to their performance, quality and manufacturing limits. Essentially, these technologies have reach their apex and further investment is based on diminishing returns to the user. A major emerging market segment today are flip-chip packages interconnectably mounted on various kinds of underlying substrates. Flip-chip technology has been implemented industry-wide because it has been found to be more than a chip interconnect system. It also provides much of the semiconductor package functions including electrical connection, thermal dissipation, mechanical support and reliability enhancement.
A number of standard interconnect packages may be used with flip-chips for single-chip modules (SCM) and, with package modifications, multi-chip modules (MCM). Some of these standard packages include the following: Ball Grid Arrays (BGA), either Plastic Ball Grid Arrays (PBGA) or Ceramic Ball Grid Arrays (CBGA), Pin Grid Arrays (PGA) and Ceramic Quad Flat Packs (CQFP). A discussion of newer interconnection technologies, such as BGA, PGA and the like, is set forth in commonly owned U.S. Pat. No. 5,381,848, which is incorporated herein by reference.
BGA's typically comprise a pattern of electrically conductive traces printed, plated or deposited onto a semiconductor package substrate ceramic or laminated PC board substrate. These BGA conductive traces branch out into an array pattern on the semiconductor package substrate surface. A semiconductor die is then mounted onto one side of the substrate and is electrically connected to these conductive traces. The BGA array pattern can be on the same side of the substrate where the semiconductor die is mounted, or on the opposite side, or on both sides.
Solder balls, which can be any one of a number of conductive alloys, are reflow soldered to the end of the conductive traces or "pads" in the array pattern. The solder balls provide the means for electrically connecting the conductive traces to the system in which it functions. Several methods are currently used to mount the solder balls onto the BGA package substrate. In one such method, soldering flux is applied to the package pads, after which a fixturing device or pickup and placement head is used to place the preformed solder balls, individually or en mass, onto the pads. The package is then heated to the melting point of the solder alloy, which then wets and bonds to the package pads.
Another method uses a printing or dispensing fixture or process to apply measured quantities of solder paste, a mixture of fine solder particles in a paste flux vehicle, onto the package contact pads. The paste can be melted by itself to form the ball contacts, or, by placing preformed solder balls into the solder paste, used to attach the preformed solder balls to the package pads. In either case, these soldering methods, and others, require a flux to achieve a satisfactory wetting of the surface by the molten solder.
During IC assembly process, flip-chip packages on laminate structures undergo "package warpage" due in great part to the heat generated during that process. In package warping, the flat surfaces of the laminate structures become undulated causing die cracks and open joints to be formed. This is a particular problem with new laminate materials which have an even thinner structural form and exhibit this package warpage problem to an even greater extent. Typically, package warpage occurs during the flip chip reflow process, the underfill epoxy cure process, and the BGA attachment process, when thermal energy is generated but the heat produced thereby is not successfully dissipated.
Therefore a need exists for providing a system and a method for producing semiconductor packages which are interconnectably mounted on underlying substrates wherein the above-described package warpage problem has been substantially minimized.